Automatic Implementation of Secure Silicon (AISS)

Mr. Serge Leef For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use.

This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. More